Shear-induced particle diffusivities from numerical simulations

Using Stokesian dynamics simulations, we examine the flow of a monodisperse, neutrally buoyant, homogeneous suspension of non-Brownian solid spheres in simple shear, starting from a large number of independent hard-sphere distributions and ensemble averaging the results. We construct a novel method for computing the gradient diffusivity via simulations on a {\em homogeneous} suspension and, although our results are only approximate due to the small number of particles used in the simulations, we present here the first values of this important parameter, both along and normal to the plane of shear, which have ever been obtained directly either experimentally or numerically. We show furthermore that, although the system of equations describing the particle motions is deterministic, the particle displacements in the two directions normal to the bulk flow have Gaussian distributions with zero mean and, a variance which eventually grows linearly in time thereby establishing that the system of particles is diffusive. In addition we show that although the particle evolution equations are, in principle, reversible, the suspension has in fact a finite correlation time $T_c$ of the order of the inverse shear rate. For particle concentrations up to 45%, we compute the corresponding tracer diffusivities both from the slope of the mean square particle displacement as well as by integrating the corresponding velocity autocorrelations and find good agreement between the two sets of results.Comment: 51 pages ; 16 figures ; 5 tables; submitted to J.Fluid Mec

The GBT: A proposed architecure for multi-Gb/s data transmission in high energy physics

The future upgrade of the LHC accelerator, the SLHC, will increase the beam luminosity by a factor of ten leading to a corresponding growth of the amounts of data to be treated by the data transmission and acquisition systems. The development of the GBT chipset addresses this issue providing a means to increase the bandwidth available to transmit data to and from the counting room. The GigaBit Transceiver (GBT) architecture will provide the support to transmit simultaneously the three types of information required to run an experiment in a hostile radiation environment over a multipurpose link. This paper describes the GBT link architecture and some aspects of its implementation. As this project is still in the specification phase, detailed features might change prior to the final silicon fabrication

An 80 Mbit/s radiation-tolerant optical receiver for the CMS digital optical link

The CMS tracker slow control system will use approximately 1000 digital optical links for the transmission of timing, trigger and control signals. In this system, the 80 Mbit/s optical receiver at the detector end of each optical link has to be radiation hard since it will operate in the severe radiation environment of the CMS tracker (10 Mrad in 10 years). We have developed a prototype circuit in a 0.25 mu m commercial CMOS process using radiation tolerant layout practices to achieve the required radiation tolerance. This effective technique consists in the systematic use of enclosed (edgeless) NMOS transistors and guardrings, and relies in the natural total dose hardness of the thin gate oxide of deep submicron processes. The circuit features an automatic gain control loop allowing detection of wide dynamic range input signals (-20 to -3 d Bm) with minimum noise, compatible with the maximum expected radiation-induced drop in quantum efficiency of the PIN photodiode. A second feedback loop compensates a photodiode leakage current up to 100 mu A, and the circuit outputs an LVDS signal. Four receiver channels were integrated in a 2*2 mm/sup 2/ chip, out of which two were simultaneously bonded to two PIN photodiodes, and their BER performance was measured before and after an irradiation with 10 keV X-rays up to 20 Mrad (SiO/sub 2/). (11 refs)

Development of SEU-robust, radiation-tolerant and industry-compatible programmable logic components

Most of the microelectronics components developed for the first generation of LHC experiments have been defined and designed with very precise experiment-specific goals and are fully optimized for these applications. In an effort to cover the needs for generic programmable components, often needed in the real world, an industry-compatible Programmable Logic Device (PLD) and an industry-compatible Field-Programmable Gate Array (FPGA) are now under development. This effort is targeted to small volume applications or to the cases where small programmable functions are required to fix a system application. The PLD is a fuse-based, 10-input, 8-I/O general architecture device compatible with a popular commercial part, and is fabricated in 0.25 μm CMOS. The FPGA under development is instead a 32 × 32 logic block array, equivalent to 25k gates, to be fabricated in 0.13 μm CMOS. The work focusses on the design of SEU-robust registers which can be employed for configuration storage as well as for user data flip-flops. The SEU-robust registers were tested in a heavy-ion beam facility; test results are presented